The present invention relates to switching circuits and semiconductor devices for switching signals in, for example, mobile communication equipment.
In recent mobile communication systems typified by cellular phones, expectations for radio-frequency (RF) switches with high performance using field effect transistors (FETs) have been growing. However, the RF switches using FETs have a drawback in which their RF characteristics deteriorate at the input of high power. To eliminate this drawback, a technique of connecting a plurality of FETs in series has been adopted. In addition, to reduce the size and cost of a semiconductor chip, a technique of using a multi-gate FET including a plurality of gate electrodes between a drain electrode and a source electrode is proposed instead of the technique of connecting a plurality of FETs in series.
Now, a conventional method for improving RF characteristics of an RF switching circuit using a multi-gate FET will be described with reference to the drawings (see Japanese Unexamined Patent Publication (Kokai) No. 2000-183362).
FIG. 17 illustrates a layout of a switching circuit constituted by a dual gate FET on a semiconductor substrate according to a conventional example. FIGS. 18A and 18B illustrate cross-sectional structures taken along the lines XVIIIa—XVIIIa and XVIIIb—XVIIIb, respectively, in FIG. 17.
As shown in FIG. 17, two ohmic electrodes 4A and 4B are formed and spaced from each other on an active layer 3 provided on a semiconductor substrate 2. Two gates 5A and 5B as Shottkey electrodes are formed between the ohmic electrodes 4A and 4B. The gates 5A and 5B are connected to respective gate pads 6. An inter-gate region 3A, which is the region between the gates 5A and 5B on the active layer 3, is connected to the ohmic electrode 4A via a connection pattern 7.
Now, it will be described how the switching circuit of the conventional example operates. Suppose a high-level voltage for turning the FET ON is 3 V, which is equal to a power supply voltage, and a low-level voltage for turning the FET OFF is 0 V, which is equal to a ground voltage. Then, when 3V is applied to the ohmic electrodes 4A and 4B and 0 V is applied to the gates 5A and 5B by way of the gate pads 6, depletion layers 8a are formed in parts of the active layer 3 under the respective gates 5A and 5B as shown in FIG. 18A. Accordingly, channel is closed, so that the FET is turned OFF.
In the switching circuit shown in FIG. 17, a direct-current (DC) potential at the inter-gate region 3A between the gates 5A and 5B is substantially equal to a DC potential at the ohmic electrode 4A by the connection pattern 7. Accordingly, the gates 5A and 5B are reverse biased, so that the depletion layers 8a more readily expand than in a case where the connection pattern 7 is not provided. At this time, depletion-layer capacitances C11a through C14a are the same. As a result, isolation to an RF signal between the ohmic electrodes 4A and 4B is enhanced.
However, a voltage applied to the ohmic electrodes during actual operation of the FET is not equal to the power supply voltage and is approximately 90% of the power supply voltage because of the influence of a voltage drop. In addition, the resistance value of the inter-gate region 3A is larger than that of the ohmic electrode 4A by about two orders of magnitude. Accordingly, the gates of the FET in the OFF state are not sufficiently reverse biased at the line XVIIIb—XVIIIb apart from the connection pattern 7, so that insufficient depletion layers 8b are formed as shown in FIG. 18B. This makes the depletion-layer capacitances C11b and C14b smaller than the depletion-layer capacitances C12b and C13b. As a result, the isolation to an RF signal becomes insufficient.
In a case where the depletion layers formed in regions under the gates expand insufficiently, the OFF state of the RF switching circuit is not maintained when a relatively-low signal is input, so that waveform distortion occurs. As a result, there arises a problem in which this waveform distortion increases harmonic distortion.
On the other hand, in a case where a bias voltage is directly applied to the ohmic electrodes and the potentials at the ohmic electrodes are fixed at the power supply voltage, the gates are sufficiently reverse biased in the OFF state where the ground voltage is applied to the gates. In this case, however, in the ON state where the power supply voltage is applied to the gates, the potential difference between each of the gates and the source is 0 V and an insufficient forward bias voltage is generated. Accordingly, there arises another problem of a large insertion loss in this ON state.